Modern electronic devices, especially those that operate on batteries, are typically designed with power savings in mind. Desktop computers generally switch into standby mode after a period of inactivity, display monitors go into sleep mode also after periods of inactivity, mobile phones collapse most non-essential functionality when not in use, and so on. However, while powering-down to enter this suspended state, many devices still expend a nontrivial amount of power maintaining nonvolatile memory. Much of this power expense is a result of current leakage across semiconductor devices that simply cannot complete shut down. While this power cost limits the overall power savings for devices connected to A/C power outlets, the power cost to battery-powered devices is battery time, which seriously affects the functional reliability of the device.
A challenge is that, when mobile devices are powered-down into a power-saving mode, users want the device to retain its state from when the power-savings mode was entered. This state information is typically maintained using latches and flip-flops within the core network of the device. The core network of a device is generally considered the circuitry that operates the core functionality of the device. The device will also usually have an input/output (I/O) network, which handles all external communication between the device and external components or devices. The core network will communicate with the I/O network in order to transmit or receive signals external to the device. Often times, the I/O network will operate at a different, higher voltage level than the core network. In such instances, the core network communicates with the I/O network through multiple level shifters.
Instead of keeping state information internally within the core network, the state information could alternatively be placed into external memory, i.e., a dynamic random access memory (DRAM), or non-volatile memory or the like. However, the device will generally use power to drive the I/O network when writing the state information to the DRAM, and the DRAM itself will still use power to maintain and refresh the memory content. Thus, external state maintenance does not typically offer any power-saving advantages over internal storage. Moreover, not all state information is stored within registers that are architecturally visible, i. e., can be accessed for reading and writing.
Two methods that have been implemented for core network state storage are (1) to scan the state into an on-chip (i.e., core network) memory; or (2) to use latches and flip-flops. Both methods provide for the device to be shut-down or power collapsed in general. However, both methods also maintain power to either the on-chip memory or latch to preserve the state stored in those components. In order to maintain power to these components, a second power source or power rail is generally provided. Shutting down or collapsing the power may be performed by disconnecting the power supply using a switch, such as a complementary metal-oxide-semiconductor (CMOS) transistor switch, or by collapsing the main supply voltage (referred to herein as VDD) to ground. Because of the limits in CMOS and other transistor technologies, current leakage typically occurs because a potential will still exist across the CMOS switch even though VDD has been disconnected or is now at ground. Therefore, even when the device is powered-down power is being drained from the battery.
Turning now to FIG. 1A, a circuit diagram of a typical flip-flop 10 is illustrated. Flip-flop 10 is a typical master-slave configuration having a functional test mode multiplexer 100 at the front end. Depending on the input to the functional test mode multiplexer 100, either the scanned in (Si) or functional (D) path will be selected. The scan-elect signal, SE, and its inverse, SEN, are provided as input to the multiplexer 100 as received from the scan-elect circuit 106. The multiplexer 100 is coupled to a master latch 101 which is coupled to a slave latch 102. The master and slave latches 101-102 typically operate on opposite phases of the clock. The control circuitry 104 uses the clock signal, Clk, to generate the two internal clock phase signals, Ck and CkN, for driving the flip-flop 10. An output 103 provides the output signal, Q, and its negative, Q-BAR.
The control circuitry 104 and retainer circuitry 105, which is made up of the slave latch 102 and a three-state device 107, are the retain-state components and are, thus, always-on, even when the rest of the circuit 10 is collapsed or powered-down. As such, the control circuitry 104 and retainer circuitry 105 are powered by VDD-Retain (FIG. 1B), while the remainder of the components of the circuit 10 are powered by VDD (FIG. 1B).
In operation, the master latch 101 is set with a state through operation of the multiplexer 100. The slave latch 102 is then set with the state from the master latch 101. When power is shut down, all of the components except the control circuitry 104 and the retainer circuitry 105 lose their respective power connections to VDD. VDD—Retain, however, maintains power to the control circuitry 104 and retainer circuitry 105. Therefore, the slave latch 102 retains the state of the master latch 101 even though the master latch 101 is now not connected to power. When the device, in which the flip-flop 10 is located, powers back on, the state information from the slave latch 102 does not directly get set back in master latch 101. In a typical configuration, flip-flops, such as the flip-flop represented by the flip-flop 10, are coupled in series. When the power comes back up in the device, the Retain-BAR signal triggers a transparency of the master latch 101. Therefore, the state information in the slave latch 102 is propagated down the series to the next flip-flop, which sets the state in the master latch of that flip-flop. In final “wake-up” operation, the master latch 101 eventually is reset to the appropriate state through the wake-up state propagation.
FIG. 1B is a pin diagram illustrating a flip-flop package 11 containing the flip-flop 10 (FIG. 1A). Because parts of the flip-flop 10 are always on, the flip-flop package 11 uses two power supplies, VDD 107 and VDD—Retain 108. There is also a connection terminal for VSS 115, which may be connected to ground. The retain-BAR signal 109 is the input to the flip-flop package 11 that affects the control circuitry 104 (FIG. 1A) when power-restore occurs and the state is being restored. A data (D) input 110 is the functional input to the flip-flop 10. The clock (Clk) input 111 is the external clock input provided to the flip-flop package 11 used in the control circuitry 104 for driving the flip-flop 10. A scan-elect (SE) control input 112 is used in a scan-elect circuit 106 to provide selections with the multiplexer 100 (FIG. 1A). Finally, output terminals, Q 113 and Q-BAR 114, provide the desired flip-flop output based on the functional input to the flip-flop package 11.
This arrangement reveals another shortcoming with the current methods, namely increasing the complexity of the semiconductor chip fabrication. A second, separate power rail or power supply, such as VDD—Retain 108 (FIG. 1B), uses extra manufacturing steps for metallization layers connecting the second power source with the appropriate circuit elements in addition to the control signaling network for controlling the second power source. All of this additional processing costs the manufacturer money.
FIG. 2A is a circuit diagram illustrating another typical flip-flop 20. The flip-flop 20 illustrates another typical master-slave flip-flop configuration. A functional test mode multiplexer 200 selects either the scanned-in or data paths to feed a master latch 201. The master latch 201 then feeds its state into the slave latch 202. The flip-flop 20 includes another latch, a retain latch 203, that obtains the current state information from the slave latch 202. Thus, the retain latch 203 is impressed with the state information from the slave latch 202. An output circuit 204 provides the resulting flip-flop alternative outputs of Q and Q-BAR. A clock circuit 205 accepts the external clock signal (Clk) as input and produces both the internal clock signals, CkN and Ck. A scan-elect circuit 206 provides both SE and SEN for operation of the flip-flop 20.
The configuration of the flip-flop 20 places the state-retention circuit, the retain latch 203, outside of the critical path of the flip-flop 20. The critical path is the main path from the multiplexer 200 through the master and slave latches 201 and 202 and then to the output 204. Control of the retain latch 203 is effected by the save circuitry 207 and the restore node 209. The save circuit 207 provides both Save and Save-BAR signals to the operation of the flip-flop 20. Save and Save-BAR operate to write the current state into the retain latch 203 from the slave latch 202. When the flip-flop 20 is powered down, all power is taken off from everything except the save circuitry 207 and the retain circuitry 208, which comprises the slave latch 203 and the circuit 210. The save circuitry 207 and the retain circuitry 208 are always-on receiving power from VDD—Restore (FIG. 2B). When the flip-flop 20 is powered-up, input of Restore and NRestore signals trigger the three-state device 209 to impress the saved previous state back onto the master latch 201.
In designing the components for the existing flip-flops, such as those illustrated in FIGS. 1A, 1B, 2A, and 2B, the devices themselves may also be more expensive when the application suggests using higher threshold-voltage devices. The always-on components, i.e., the control circuitry 104 and the retainer circuitry 106 in FIG. 1A and the save circuit 207 and the retain circuitry 208 in FIG. 2A, are often selected to be more robust and capable of handling higher voltages without leaking. In general, CMOS technology can be manufactured in essentially three “grades”: high threshold voltage (HVT), normal threshold voltage (NVT), and low threshold voltage (LVT). The higher the threshold voltage, the less current leakage will typically result when the transistor is “off.” HVT CMOS is usually more expensive than NVT or LVT. Thus, if a manufacturer attempts to reduce the power leakage by building the critical “always-on” components in these devices from HVT CMOS, there is added expense there as well.
FIG. 2B is a pin diagram illustrating a flip-flop package 21 containing the flip-flop 20 (FIG. 2A). Because parts of the flip-flop 20 are always on, the flip-flop package 21 uses two power supplies, VDD 107 and VDD—Retain 108, as with the flip-flop package 11 (FIG. 1B). The flip-flop package 21 also includes the VSS 115 terminal. An NRestore signal 211 is the input signal used on power-up, when directing the save circuitry 208 (FIG. 2A) to impress the saved state information back onto the master latch 201 (FIG. 2A). A data (D) input 110 is the functional input to the flip-flop 20. A clock (Clk) input 111 is the external clock input provided to the flip-flop package 21 used in the control circuitry 104 for driving the flip-flop 20. The scan-elect (SE) control input 112 is used in the scan-elect circuit 106 to provide selections with the multiplexer 200 (FIG. 2A). Output terminals, Q 113 and Q-BAR 114, provide the desired flip-flop output based on the functional input to the flip-flop package 11. Unlike the flip-flop 10 (FIG. 1A), the flip-flop 20 uses Save and SaveN signals to control the saving of the state information into the retain latch 203. Thus, the Save input 212 provides this input into the flip-flop package 21.